1. Field of the Invention
The present invention relates the field of programmable logic arrays (PLAs), and more particularly relates to high performance PLAs utilized in applications requiring a minimal power consumption.
2. Background Art
PLAs have been used for decades to efficiently implement logic in circuit design. PLAs are widely used, for example, in integrated circuits making up the component parts of computers, including personal computers.
Recently, the market place for personal computers has been demanding ever smaller and more portable personal computers. Such portable computers are typically powered by batteries. This has been feasible using CMOS technology integrated circuits using traditional circuit designs, since CMOS technology is inherently a relatively low power technology, compared, for example, to bipolar circuit technology.
However, personal computers implemented in traditional CMOS circuitry nonetheless still consume enough power to discharge batteries in a period of time short enough to be considered undesirable. One of the sources of this excessive power consumption is the aforementioned PLAs.
FIG. 1 shows a conventional static PLA implemented in CMOS in a Static NOR-NOR configuration with grounded pull-up P type devices to achieve high density. This approach provides the smallest layout area for the PLA in CMOS, and provides excellent performance, but consumes considerably more DC power than a conventional CMOS dynamic PLA implementation, as is known.
Attempts have been made to lower the power consumption requirements of high performance PLAs of this type. For example, U.S. Pat. No. 4,761,769, entitled "MOS Read Only Memory Device," which issued Aug. 2, 1988, and was assigned to Oki Electric Industry Co., Ltd., discloses a PLA having a clock signal generator circuit for generating a pair of positive and negative clock signals by detecting a change in the input signal to the PLA. In response thereto, a charging control circuit arrangement powers up the array. In this way, it is claimed that power consumption is reduced because the PLA is only powered up when needed. However, even this arrangement results in unacceptable power consumption for battery powered computers.
Other references in the general field are U.S. Pat. No. 5,045,726, entitled, "Low Power Programming Circuit For User Programmable Digital Logic Array," which issued Sep. 3, 1991, to North American Phillips Corporation, and which discloses a user programmable PLA comprising a plurality of bipolar transistors arranged in respective rows and columns. Programming current of sufficient magnitude is provided to selected rows and columns to cause a fused connection to be made, thereby characterizing the PLA. The circuit is configured such that row drivers and transmission gates only draw quiescent operating current in operation if the associated link has been previously fused.
U.S. Pat. No. 5,033,017, entitled "Programmable Logic Array With Reduced Power Consumption," which issued on Jul. 16, 1991, and was assigned to Fujitsu Limited and Fujitsu Micro Computer Systems Limited, discloses a PLA having a precharge and discharge arrangement which operates in synchronism with a clock signal supplied thereto. A circuit is provided that holds the programmable logic array in a precharged state by setting the clock signal to a fixed level when the PLA is not selected.
U.S. Pat. No. 4,697,105, entitled "CMOS Programmable Logic Array," which issued on Sep. 29, 1987 and was assigned to the American Telephone and Telegraph Company, AT&T Bell Laboratories, discloses a PLA including a dynamic AND plane and an OR plane using clock load devices. The high precharged voltage state in the AND plane places the logic lines in the OR plane in a low voltage state during precharge. The OR logic lines may then be pulled to a high level during the decode operation. A clock having a delay path is used to control the precharge and decode operations of the PLA.
Finally, U.S. Pat. No. 4,814,646, entitled "Programmable Logic Array Using Emitter-Coupled Logic," which issued on Mar. 21, 1989 and was assigned to Monolithic Memories, Inc., discloses an ECL PLA in which various expedients allegedly produce lower power operation, including the provision of a switched current source pull-down means for pulling down the rows of the PLA array, and by allowing each pair of output terminals to share a predefined set of product terms.
None of the above arrangements provide the desired level of low power operation, combined with high performance operation of the PLA.